1. Field of the Invention
The present invention relates to an integrated circuit, and more particularly, to an integrated circuit capable of locating failure process layers on a chip.
2. Description of the Related Art
For logic process debugging, memory and FPGA are usually selected. Fault isolation can be achieved through a simple bit mapping process, and further, fault isolation to locate appropriate failure process layers is also possible using the bit map signature. However, fabless ASIC companies do not have such kind of products for new process debugging and yield learning, resulting in a long learning curve for yield enhancement. Further, fabless ASIC companies must cooperate with foundry fabs closely for process debugging or development, for example accepting products on wafers having passed WAT (wafer acceptance test) of foundry fab. Unfortunately, products sometimes still experience poor yield caused by process problems. Fabless ASIC facilities currently do not have effective methods and products for fab process debugging, especially in backend process learning.